The present invention is related to video display devices, and particularly to generating and displaying an emulation signal by a three dimensional (3-D) emulation display device.
3-D emulation devices, or stereoscopic image projectors, generally include a video screen and associated shutter glasses. The shutter glasses are adapted to be head worn by the user. Generally, the screen is rigidly coupled to the shutter glasses so as to maintain alignment of the screen and the user field of view. The screen provides a sequence of alternating images corresponding to a right eye view and a left eye view. The shutter glasses are adapted to alternate between blocking the view of the right eye and of the left eye according to synchronization with the screen so as to allow for delivering a right view image to the right eye and a left view image to the left eye. The right eye view and left eye view images can be generated by various methods including digital transformation of a two dimensional video, generation of a dual view digital video by a video processor, or by employing a stereoscopic video camera.
The shutter lenses of the shutter glasses must operate at a very high frequency so as to avoid image flicker and noticeable degradation. Such frequency is ordinarily greater than 120 Hz, which is double the standard rate of 60 Hz. Furthermore, the corresponding video data is synchronized to be delivered at the shutter frequency. Thus, the video data display consumes substantial power and imposes a limiting factor on image resolution.
The shutter glasses commonly employ LCD shutters to provide electronically controlled shutter operation. However, the slow LCD response time, even at the low frequency of 120 HZ, causes some image degradation. Thus, there is a need for a system and method for delivering 3D stereoscopic video, which reduces power consumption and improves image quality.
In accordance with the present invention there is presented an emulation device adapted to receive a single channel of data, which includes data for both a left eye view and for a right eye view, and display the data on corresponding left eye and right eye displays of the device.
In one embodiment, the invention provides a method for delivering a video signal to a three dimensional emulation device having a left display associated with a left display view and a right display associated with a right display view. The method includes receiving an emulation signal, which includes frame data alternating between frame data for the left display view and frame data for the right display view. The method provides the emulation signal to the left display and to the right display. The method provides an enable signal to the left display and to the right display. The enable signal has a first state over a period corresponding to the frame period and has a second state over a subsequent period corresponding to the frame period. The enable signal is also synchronized with the emulation signal to provide the first state when the emulation signal provides the left view data and to provide the second state when the emulation signal provides the right view data. Accordingly, the left display is adapted to refresh display data in response to the first state of the clock signal and the right display is adapted to refresh display data in response to the second state of the clock signal.
In another embodiment, the invention provides a method for providing emulation video data to a 3-D emulation display device having a right display and a left display. The method includes receiving video frame data having a frame period. The method transforms frame data to generate an emulation signal, which includes consecutive frame data alternating between a left view transform and a right view transform of video frame data. The method provides the emulation signal to the right display and to the left display. Finally, the method provides an enable signal to right display and to left display. The enable signal has a first state over a time corresponding to a frame period and a second state over a time corresponding to a subsequent frame period. Therefore, the left display is adapted to update the frame data in response to the first state of the enable signal and the right display is adapted to update frame data in response to the second state of the enable signal. The enable signal is provided in synchronization with the emulation signal whereby the first state of the enable signal corresponds to the emulation signal providing left view data and the second state of the enable signal corresponding to the emulation signal providing right view data.
In yet another embodiment, the invention provides an emulation video signal display system. The system includes a video processor having a video output and a synchronization output. The video processor provides an emulation video signal to the video output. The emulation video signal includes frame data alternating between frame data for a left display view and frame data for a right display view. The emulation video signal provides each frame data over a frame period. The system also includes an enable signal generator having a control input and an enable output. The control input is coupled to the synchronization output of the video processor. The enable output provides an enable signal having a first state over a period corresponding to the frame period and having a second state over a subsequent period corresponding to the frame period. The enable signal is synchronized with the emulation signal to provide the first state when the emulation signal provides frame data for the left display view and to provide the second state when the emulation signal provides frame data for the right display view. The system further includes a first memory element having a data input, an update input, and a data output. The data input is coupled to the data output of the video processor to receive the emulation signal. The update input is coupled to the enable output of the enable signal generator. The first memory is adapted to update data in response to the first state of the enable signal. The system includes a second memory element having a data input, an update input, and a data output. The data input coupled to the data output of the video processor to receive the emulation signal. The update input coupled to the enable output of the enable signal generator. The second memory is adapted to update data in response to the second state of the enable signal. Finally, a left display has a data input coupled to the data output of the first memory element and a right display has a data input coupled to the data output of the second memory element.